5-stage instruction cycle (Computer science)

Assume we use a pipeline with a 5-stage instruction cycle:

1. IF=InstructionFetch
2. ID=InstructionDecode
3. EX=Execute
4. MEM=Memoryaccess
5. WB=Registerwriteback

Consider the following sequence of instructions (the final register in each instruction is where the value computed is stored):

1: ADD R1, R2, R1
2: INC* R5, R5
3: ADD R2, R5, R5
4: SUB R1, R3, R3
5: ADD R3, R4, R4

*Increment by one, ie +1 to R5

1. (a)  Assume that the pipeline does not use operand forwarding and that the only sources of pipeline stalls are the data hazards. Draw a multi-cycle pipeline diagram to show the execution of the five instructions listed above.
2. (b)  How long does it take for the instruction sequence to complete?
3. (c)  Can you reorder the instructions such that they give the same results and stalls are reduced or eliminated? Justify your answer.

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Answers required for part (a) part (b) and part (c)

Reference book: Stallings, W. Computer organization and architecture: designing for performance (Pearson Education, 2015) 10th global edition [ISBN 9781292096858 (pbk)]