i. ADD R1,R2,R1
LW R2, 0(R1)
LW R1, 4(R1)
OR R3, R1, R2
ii. LW R1,0(R1)
AND R1, R1, R2
LW R2, 0(R1)
LW R1, 0(R3)
a) Find all data dependences in this instruction sequence.
b) Find all hazards in this instruction sequence for a 5-stage pipeline with and then without forwarding.
c) To reduce clock cycle time, we are considering a split of the MEM stage into two stages. Repeat (b) for this 6-stage pipeline.
Question 2 (6 pts) This exercise is intended to help you understand the relationship between forwarding, hazard detection, and ISA design. Problems in this exercise refer to the following sequences of instructions, and assume that it is executed on a 5-stage pipelined datapath:
Instruction Sequence
i. ADD R5,R2,R1
LW R3,4(R5)
LW R2,0(R2)
OR R3,R5,R3
SW R3,0(R5)
ii. LW R2,0(R1)
AND R1,R2,R1
LW R3,0(R2)
LW R1,0(R1)
SW R1,0(R2)
a) If there is no forwarding or hazard detection, insert NOPs to ensure correct execution.
b) Repeat (a) but now use NOPs only when a hazard cannot be avoided by changing or rearranging these instructions. You can assume register R7 can be used to hold temporary values in your modified code.
c) If the processor has forwarding, but we forgot to implement the hazard detection unit, what happens when this code executes?
d) If there is forwarding, for the first five cycles during the execution of this code, specify which signals are asserted in each cycle by hazard detection and forwarding units in Figure 4.60.
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